Abstract
Arithmetic operations are becoming a bigger concern in the digital system for applications like ALU (Arithmetic and Logic Unit) and DSP (Digital Signal Processing). Our work focuses on novel 4–2 and 5–2 Compressors(CM) applied in multiplication architectures such as Unsigned Wallace tree multiplier, Vedic mathematics using Urdhva Triyakbyam sutra, and Signed Baugh-Wooley Wallace tree multiplier, Signed Booth with Radix 2 and Radix 4. The proposed compressors architectures have shown better results when compared with the existing compressors. The ASIC design Implementation was done using Standard cell 180nm CMOS technology and the Verilog HDL code is tested in Xilinx tool, with the help of ISE Simulator (ISim).
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