ASIC design for monobit receiver

Abstract

A design for the receiver application specific integrated circuit (ASIC) is described. The receiver is a wide band (1 GHz) digital receiver designed for electronic warfare applications. The receiver can process two simultaneous signals and has the potential for fabrication on a single multi-chip module (MCM). The receiver consists of three major elements: (1) a nonlinear radio frequency (RF) front-end, (2) a signal sampler and formatting system (analog-to-digital converter (ADC) and demultiplexers), and (3) a patented monobit algorithm implemented as an ASIC for signal detection and frequency measurement. The receiver's front end, ADC and algorithm experimental performance results will be presented. The receiver uses a two-bit ADC operating at 2.5 GHz whose outputs are collected and formatted by demultiplexers for presentation to the ASIC. The ASIC has two basic functions: (1) perform a fast Fourier transform (FFT) and (2) determine the number of signals and report their frequencies. The ASIC design contains five stages: (1) the input, (2) the FFT, (3) the initial sort, (4) the squaring and addition, and (5) the final sort. The chip will process the ADC outputs in real time, reporting detected signal frequencies every 102.4 ns.