Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current

Abstract

This paper presents a new RC-based power-rail electrostatic discharge (ESD) clamp circuit, which achieves ultra-low leakage current while maintaining low silicon utilization. A capacitance-boosting technique is used in conjunction with mathematical analysis of area utilization to determine the best set of parameters to achieve the smallest implementation area in silicon. The proposed power-rail ESD clamp circuit has been verified in a 65-nm general-purpose CMOS process, which achieves an ultra-low standby leakage current of 80 nA at 25 °C under 1-V bias, as well as ESD robustness of a 4-kV human body model and a 250-V machine model with a silicon area of only $\mbox{45} \mu\mbox{m}\times \mbox{17} \mu\mbox{m}$ .