Area optimized design of tetrad flip-flop using new tetrad value logic gate’s

Abstract

Logic levels in digital systems are predefined voltage and current range and a defined difference in voltage and current value signify binary information’s in digital systems. There are many logic families available to define binary data. In binary logic, there are two logic levels 1 and 0. This paper defines a new tetrad value logic (TVL) which can have four logic levels 0,1,2 and 3. This work presented novel designs of tetrad value logic NOT gate, AND gate and OR gate. With the help of these tetrad logic gates, a tetrad logic Flip-flop has been designed and tested on Tanner Electronic Design Automation (EDA) tool. The proposed tetrad flip-flop is a memory cell of tetrad Value Logic (TVL) which can store Logic 0, Logic 1, Logic 2, and Logic 3 when the input clock is off, and on the positive edge of the input clock, it can change the past stored logic with new input logic. This work discusses the possible application of tetrad logic. Simulation of tetrad logic gates and flip flop performed with help of tanner tool and verifies expected output correctly for all possible test cases. Parameters like Voltage levels, power consumption, noise margin, MOS count, propagation time, fan-out, noise margin, clock frequency, sink, source current, setup and hold time, are analyzed for proposed tetrad logic gates and flip flop. The S-edit 9.0 is used for the schematic design and T-spice 9.0 is used for parameter setting and design technology selection and W-edit 9.0 is used for simulation observation. The obtained results have been compared with other similar work and found better.