Area Efficient Shared Diode Multi-Level Cell SOT-MRAM

Abstract

This paper proposes a diode-based multi-level cell spin–orbit torque magnetic random-access memory (SOT-MRAM) for high density memory applications. By stacking a shared diode over two in-parallel magnetic tunnel junctions (MTJs) that share a common heavy metal electrode, our proposed cell requires only one silicon-based transistor to access 2 bits. Having just one transistor to access 2 bits results in at least $2\times $ higher density when compared to various designs in the literature. Moreover, utilizing a high-density MRAM process, a $4F^{2}$ effective 1 bit area can be achieved. Furthermore, our proposed design maintains the high energy efficiency of the conventional SOT-MRAM. In addition, an improvement in figure of merit of at least 30% defined as energy area product is obtained compared to various designs. This paper also discusses the essential requirements to realize our proposed SOT-MRAM, such as the realization of diode MTJ stack and SOT-MTJs, with different critical currents and electrical resistances.