Area-efficient low power CMOS image sensor readout circuit with fixed pattern noise cancellation

Abstract

A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise (FPN) cancellation is proposed. By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling (CDS), pixel FPN is cancelled and column FPN is stored and eliminated by the sample-and-hold operation of digitally programmable gain amplifier (DPGA). The bandwidth balance technology based on operational amplifier (op-amp) sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA. The circuit is designed and simulated using 1P6M 0.18 μm 1.8 V/3.3 V process. Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV. The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated. The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS. The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB. Its power consumption is 1.4 mW, which is reduced by 57% compared with traditional schemes. The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems.