Area efficient diode and on transistor inter‐changeable power gating scheme with trim options for SRAM design in nano‐complementary metal oxide semiconductor technology

Abstract

Reducing the leakage power in embedded static random access memory (SRAM) memories is critical for low-power applications. Raising the source voltage of SRAM cells through diode transistor in standby mode reduces the leakage currents effectively. However, in order to preserve the state of the cell in standby mode, the source voltage cannot be raised beyond a certain level. To achieve that, the size of the required diode transistor becomes larger, as the supply voltage shrinks in the nano-complementary metal oxide semiconductor (CMOS) technologies. In this work, an area efficient power gating technique with capability of post-silicon trimming of the voltage across SRAM cell is presented. Proposed scheme provides many options to trim the SRAM source voltage (ranging from 50 to 150 mV in steps of 25 mV approximately.) with 3% area overhead when applied to complete SRAM bank. The scheme has been illustrated with a 16 kb SRAM macro at 28 nm CMOS technology at 0.85 V supply voltage. Sector-based power gating is presented which enables leakage savings while memory is in the active mode. The area overhead of the presented scheme is 8% when applied to SRAM bank array split into sectors.