Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution

Abstract

Application-Specific Network-on-Chip (ASNoC) has emerged as a more efficient design alternative to the regular Network-on-Chip (NoC) topologies, which can better suit the communication requirements of an application. In this work, we have proposed a three step ASNoC synthesis procedure that targets optimization of the three major design parameters – area of the chip, communication cost (CC) of the resulting on-chip network and the peak temperature of the chip (Tpeak). Inputs to the procedure are the core dimensions, corresponding average power consumptions and the core graph of the application. In the first step, an area-optimized floorplanning of the cores has been conducted. Considering an overhead constraint on the minimum area generated in this step, a communication cost aware floorplan has been generated in the second step. Finally, considering an overhead constraint on the minimum CC obtained from the second step, a thermal-aware white space allocation and redistribution (WSA&R) has been carried out. At each step, Mixed Integer Linear Programming (MILP) formulation has been made along with heuristic or meta-heuristic methods. Core placement has been performed using a Simulated Annealing (SA) based technique with its initial solution generated using a Particle Swarm Optimization (PSO) based approach. A router placement heuristic has been proposed that considers core rotation and core mirroring techniques to optimally place the primary routers. WSA&R has been performed using an iterative SA-based approach. At each stage of the design flow, we have compared our proposed method with an MILP based method and other contemporary heuristics. Significant improvements have been achieved in both CC and Tpeak. The proposed WSR method has been able to reduce Tpeak up to 22°, considering 35% overhead on CC.