Architecture exploration of QoS control Silicon Intellectual Properties for Cross-Layer Designs in wireless networks

Abstract

We propose an architecture exploration scheme for QoS control Silicon Intellectual Properties (SIPs). The scheme integrates network simulator (NS-2), embedded Linux operating system, Linux driver, Electronic Design Automation (EDA) tools, extended on-chip bus, and real Field Programmable Gate Array (FPGA) hardware for comprehension of how data bus width and clock rate affect QoS performance in wireless networks. Software and hardware co-design flow and programming paradigm for evolving the FPGA prototype toward a platform-based reusable SIP with driver and cross-layer interface are also depicted. Three QoS control experiments in video streaming over HCCA, EDCA, and WiMAX wireless technologies demonstrate the proposed exploration scheme effectively helps engineers comprehend impacts of architectural design parameters on networking performances in wireless multimedia communications.