Symbiosis in Action

Abstract

Spatial compute architectures, like Field Programmable Gate Arrays (FPGAs), constitute a key architectural pillar in modern heterogeneous compute platforms. Spatial architectures need a sophisticated Electronic Design Automation (EDA) compiler to optimally map and fit a user's workload/design onto the underlying spatial device. This EDA compiler not only helps users to custom-configure the spatial device but is also critically required for architectural exploration of new spatial architectures. The FPGA industry has had a long history of innovation in this symbiotic relationship between EDA and reconfigurable spatial architectures. This talk will walk down the memory lane of multiple waves of such innovation, amplifying how the complexity of EDA technology has not only scaled with Moore's law scaling of size and complexity of silicon hardware, but also how it has been pivotal in the architectural design of modern FPGAs. A general overview of modern FPGA EDA flows and key differences compared to Application-Specific Integrated Circuit (ASIC) EDA flows will be discussed. State-of-the-art FPGAs, Stratix® 10 and AgileX™ from Intel incorporate an advanced register-rich HyperFlex™ architecture that introduces disruptive optimization opportunities in the EDA compiler. Such physical synthesis optimization technologies like logic retiming, clock skew optimization, time borrowing, and their synergies and challenges will be discussed. Solving these challenges enables FPGAs to achieve non-linear performance improvements. Logic retiming was first introduced as a powerful sequential design optimization technique three decades ago, yet gained limited popularity in the ASIC industry, because of the lack of scalable sequential verification techniques. This talk will highlight the root causes of this issue and present innovations in retiming technology and constrained random simulation that allow the successful verification of retimed circuits, thereby enabling the use of logic retiming for FPGAs. FPGAs have traditionally targeted Register-Transfer Level (RTL) designers. To enable wider adoption of FPGAs, Intel has developed several High-Level Design (HLD) tools, frameworks, libraries, and methodologies, raising the level of programming abstraction. This talk will provide a glimpse into Intel's HLD offerings that enable software developers in the broader ecosystem to leverage FPGAs. Academic researchers will also be provided with some key research vectors to help propel the FPGA industry further.