Architecture Design of a Memory Subsystem for Massive MIMO Baseband Processing

Abstract

This brief presents an on-chip memory subsystem for massive multiple-input-multiple-output (MIMO) baseband processing at the base station. In massive MIMO systems, the required memory bandwidth and capacity are orders of magnitude higher than those used in conventional wireless systems, due to the large number of serving antennas. These are further combined with design targets on low access latency and flexibility in data organization and access modes. This brief applies and improves the concept of parallel memories to achieve the challenging design target with low hardware overhead. As a case study, a memory subsystem for 128-antenna and 16-user massive MIMO systems is evaluated using ST 28-nm technology. According to postlayout simulation results, the proposed memory subsystem provides 512-Gb/s throughput and offers 1-Mb capacity with a cost of 0.30 mm2.