Architectural Level Crosstalk Minimization: A Tool

Abstract

Design automation is one of the key requirements of today's growing ASIC/SOC design process. The era of high speed and high density designs has led the design engineers various challenges. As the technology is scaling, one of the major concerns of VLSI design is signal integrity. Crosstalk is the major cause of signal integrity that occurs due to coupling of charge between the conducting interconnects.Most of the CAD tools available in the market addresses this issue at the post layout level. But tackling crosstalk at the stage when the design is ready for fabrication may not be always feasible in terms of area and power overheads. This paper proposes a novel CAD tool which performs an optimization to crosstalk effect at architectural level using High Level Synthesis (HLS) procedures. The proposed work performs crosstalk aware simultaneous scheduling, binding and allocation of resources in the given data flow graph using hybrid genetic and simulated annealing algorithm (GASA). The data flow graph of an intended design is fed as an input to the tool and it generates corresponding crosstalk optimized verilog code as an output. The obtained design is synthesizable in any of the commercial tool. The work is tested on 3X3 matrix multiplier and experimental result shows that there is 65.07% improvement in crosstalk delay and hence the Signal Integrity. Hence this work suggests a technique for architectural level crosstalk optimization.