Approximate radix-8 Booth multiplier for low power and high speed applications

Abstract

Approximate computing is an emerging circuit design technique which reduce the energy consumption with acceptable degradation in accuracy. Three approximate radix-8 Booth multipliers are proposed in this paper to explore the advantages of approximate computing. These multipliers are designed by using two proposed approximate Booth encoders for the generation of approximate partial products. Approximate partial products are introduced into a few number of least significant columns (AC) of the partial product matrix. The proposed multipliers with 16-bit inputs are simulated using a 45-nm CMOS technology library. For AC = 16, the results indicate that the first proposed multiplier reduces power delay product (PDP) and Area by 33% and 23% respectively as compared to conventional radix-8 Booth multiplier. Moreover, it has a Normalized Mean Error Distance (NMED) of 1.43E-5. The second proposed multiplier shows 43% and 31% reduction in PDP and Area respectively with an NMED of 1.664E-5. Similarly, the third proposed multiplier shows 37% and 25% reduction in PDP and Area respectively with an NMED of 1.512E-5. The accuracy of proposed multipliers are verified with real-time applications in image processing and deep learning.