Approximate Multiplier for Power Efficient Multimedia Applications

Abstract

AbstractThe design of fast integrated circuits with less power consumption has become increasingly significant as technology advances, and chip dimensions are reduced to enable circuits with lower energy consumption. Approximate computing has risen in popularity as an intriguing option to reduce power consumption, latency, and area while losing some precision for error-tolerant applications. This paper proposed an approximate multiplier design based on a dual-stage 4:2 compressor multiplier with high-speed and low-power consumption. The compressors proposed are used to implement the 16 × 16 Dadda multiplier. The proposed design is simulated using Vivado with Artix-7 technology. The simulation findings show that the proposed approach outperforms the existing methodology in terms of various performance parameters. The total number of cells is reduced from 405 in the exact methodology to 140 in the proposed methodology, representing a 65.43% decrease and a 1.768 ns reduction in the maximum data path delay. In addition, the total on-chip power is reduced by 14.95%. The proposed circuits provide a better balance of hardware and accuracy metrics. The necessity for approximate multiplier techniques using the Verilog hardware description language (HDL) has paved the way for rapid computing in error-tolerant applications, for example, signal processing and multimedia.KeywordsApproximate computingDadda multiplierField programmable gate array