Approximate Multiplication and Division Calculation for DSP Applications

Abstract

Digital signal processing (DSP) is a promising alternative to accomplish a wide variety of signal processing operations. Multiplications and divisions have been urgently proposed to perform different DSP operations in real-time applications. However, the design and implementation of multiplication and division calculations have some limitations such as strict timing, bounded power consumption, and higher accuracy. The exact execution of these complex operations consumes great hardware resources and power consumption. Approximate computation for the main and complex arithmetic functions is a demand solution to decrease power, area, and delay. In this paper, low-power and high-accuracy approximate multiplication and division processes have been implemented using a 90 nm CMOS process, 1.0 V supply voltage standard cell library. The approximate multiplication and division algorithm depends on enhanced logarithmic converters. The logarithm-based arithmetic exhibits a good performance with decreasing the used hardware resources and runs at a higher speed. The proposed scheme achieves less hardware with minimal power consumption. The proposed approximate structure demonstrates up to a 62% saving in power with a rise in the accuracy level as compared with the prior approximate works. At the same time, the proposed multiplier and divider can carry out the multiplication and division processes in 1.8 ns, respectively.