Abstract

This paper presents the design and performance evaluation of a reduced complexity algorithm for timing synchronization. The complexity reduction is obtained via the introduction of approximate computing, which lightens the computational load of the algorithm with a minimal loss in precision. Timing synchronization for wideband-code division multiple access (W-CDMA) systems is utilized as the case study and experimental results show that the proposed approach is able to deliver performance similar to traditional approaches. At the same time, the proposed algorithm is able to cut the computational complexity of the traditional algorithm by a 20% factor. Furthermore, the estimation of power consumption on a reference architecture, showed that a 20% complexity reduction, corresponds to a total power saving of 45%.

Highlights

  • The continuous growth in demand for bandwidth and mobility has contributed, in the past decades, to the development of a wide set of communication standards

  • Providing a single architecture that can at run-time modify its behaviour and connect to different radio systems is truly appealing both for end users as well as for the industry of integrated circuits (IC): end users can benefit from it by carrying around a single device instead of a set of devices, while IC’s manufacturers can spread the design costs of a single platform over a wider range of applications

  • The complexity reduction is based on the approximate computing paradigm

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Summary

Introduction

The continuous growth in demand for bandwidth and mobility has contributed, in the past decades, to the development of a wide set of communication standards. The given flexibility can be utilized at algorithm level to enable more efficient power implementations. The aim of the design was to reduce the computational complexity while maintaining the overall performance at an acceptable level by dynamically adapting the matched-filter performance according to the estimated signal-to-noise-ratio (SNR).

Results
Conclusion

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