Applying stochastic modeling to bus arbitration for systems-on-chip

Abstract

In this article we implement a stochastic modeling technique for simulating the communication between processors and arbitration among buses for an embedded SoC. The stochastic models implemented with queues have been used to estimate, through simulation of different arbitration policies, the power consumption and delays, as well as estimate average or worst case scenarios that could occur with different architectures and arbitration policies . This idea could then be extended to writing probabilistic test benches to analyze the performance of different architectures as well as device and test arbitration policies which would attempt to optimize the power consumption and buffer lengths with constraints on the average delay.