Application of Taguchi Method in Designing a 22nm High-k/Metal Gate NMOS Transistor

Abstract

This paper reports on the application of Taguchi method in modelling a 22nm gate length high-k/metal gate NMOS transistor. The Nominal-the-Best Signal-to-noise Ratio (SNR) using Taguchis optimization technique was utilized to optimize the process parameters in determining the best threshold voltage (Vth) value where it was used as the evaluation variable. The high permittivity material (high-k) / metal gate device consists of titanium dioxide (TiO2) and tungsten silicide (WSix) respectively. The simulation work was executed using a TCAD simulator, which consist of ATHENA and ATLAS as a process and device simulator respectively. In this research, the Halo implantation tilting angle was identified as the most influencial factor in affecting the Vth with a percentage of 87%, followed by the oxide growth anneal temperature (8%), the metal gate anneal temperature (4%) and lastly the Halo implantation dose (1%). As a conclusion, the Halo tilting angle is the dominant factor in optimizing the process parameter. Meanwhile the Halo implantation dose can be considered as an adjustment factor in order to achieve the target Vth value of 0.289 V which is in line with projections made by the International Technology Roadmap for Semiconductors (ITRS).