Application of nanosphere lithography to charge trap flash memories with patterned Si3N4 trap layers

Abstract

Graphical abstractDisplay Omitted Highlight? Nanosphere lithography is applied to the charge trap flash memories. ? A 500-nm-diameter polystyrene bead array was used as a mask to make patterns. ? The pattern depth measured by atomic force microscope was about 4 nm. ? The patterned MANOS capacitor shows a good memory characteristics. In this paper, nanosphere lithography (NSL) is applied to the surface of the Si3N4 trap layer in the charge trap flash device to improve its memory characteristics. A 500-nm-diameter polystyrene bead array was used as a mask to make patterns on the surface of the Si3N4 trap layer during etching processes using CF4 gases. The pattern depth measured by atomic force microscope was about 4nm. The metal-aluminum oxide-nitride-oxide-silicon capacitor that has a patterned surface shows a larger capacitance-voltage memory window of 5V, higher tunneling current at bias voltages higher than 10V, and faster program speeds of 50ms, as compared to those measured from the capacitor with the flat surface. These results are thought to be due to abundant memory traps available at the interface between the nitride and top oxide formed by NSL.