Application of Molecular Dynamics Simulations to Plasma Etch Damage in Advanced Metal-Oxide-Semiconductor Field-Effect Transistors

Abstract

According to international technology roadmap for semiconductors (ITRS) (SIA, 2009), the shrinkage of silicon-based metal–oxide–semiconductor field-effect transistor (MOSFET) – an elemental device (unit) in ultra-large-scale integrated (ULSI) circuits – has been accelerating due to expanding demands for the higher performance and the lower power operation. The characteristic dimensions of current MOSFETs in mass productions are around 30 – 50 nm. Figure 1 shows the scaling trend of the key feature sizes in ULSI circuits predicted by Semiconductor Industry Association, USA. Various types of MOSFETs are designed for the specific purposes, i.e., low standby power (LSP), low operation power (LOP), and high performance (HP) operations, and built in ULSI circuits such as dynamic random access memory (DRAM) and micro-processing unit (MPU). New structured MOSFETs such as fully-depleted (FD) and metal-gate (MG) devices have been recently proposed. Since physical gate length (Lg) and source / drain extension depth (Ext) are the key feature sizes determining MOSFET performance (Sze & Ng, 2007), the shrinkage of Lg and Ext is a primal focus in the development of MOSFETs. These sizes have become a few nanometers, comparable to the scale of atomistic simulation domain.