Abstract
The APES system for the design and evaluation of VLSI or WSI array processors is presented. APES makes it possible to study fault-tolerant array architectures and methodologies by simulating the behavior of the system when faults occur: the type and distribution of faults can be defined by the designer. A diagnostic tool is integrated in APES to evaluate the fault-detection and error-correction capabilities of the system under observation. Another tool makes it possible to perform and evaluate the array reconfiguration after fault occurrence by adopting a user-defined strategy. Features including data entry (using a graphic editor or a hardware description language), the simulation engine, the fault injector, the diagnostic evaluator, and the restructuring/reconfiguration manager are discussed. >
Published Version
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