Abstract
The paper deals with challenges in the modeling of high voltage JFET. As the most important, the effect of pinch-off voltage and related issues are discussed here. The pinch-off voltage in the traditional SPICE compact JFET model is only considered as a drop in the drain-source current, while other phenomena, such as capacitance sharp drop, or punch-through between gate and substrate are completely ignored. The traditional compact JFET model does not even consider the gate as isolated from substrate. In this paper, an implementation of a dual-gate JFET model is discussed with a special emphasis on pinch-off voltage and related effects.
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