Anomalous Behavior of Gate Current and TDDB Lifetime by Constant Voltage Stress in NO-Annealed SiC-MOSFETs

Abstract

Silicon-carbide metal–oxide–semiconductor field-effect transistors (SiC-MOSFETs) are core devices for future power electronics. The factors limiting their automotive applications are currently under investigation. Postoxidation annealing in NO gas is a key technology to achieving high carrier mobility in SiC-MOSFETs. In this article, we study the NO annealing effects on time-dependent dielectric breakdown (TDDB) reliability by the constant voltage stress (CVS) method at room temperature (RT). We show that heavy NO annealing enhances hole trapping near the SiO2/SiC interface and leads to a rapid increase in the gate current ( $I_{\text {g}}$ ) and results in shorter time-to-breakdown ( $t_{\text {BD}}$ ) and smaller Weibull slope of $t_{\text {BD}}$ in comparison to light NO annealing case. However, the detailed examination of the $I_{\text {g}}$ behavior reveals that the charge-to-breakdown ( $Q_{\text {BD}}$ ) and its distribution do not deteriorate. Therefore, we must reconsider the use of the CVS method by examining the $I_{\text {g}}$ behavior during stress, which strongly depends on NO annealing conditions.