Annealing effects of polycrystalline silicon gate on electrical properties of thin gate oxide

Abstract

A study of annealing effects on micro-structures and electrical properties of an initially amorphous silicon gate and of thin gate oxide was carried out. The amorphous silicon gate was crystallized by post gate anneal. As the annealing temperature increases, the resistivity of gate decreases due to the increase of dopant activation rate. The strong compressive stress in amorphous silicon gate is relaxed as the micro-structure of the gate changes to polycrystalline silicon. The electrical properties of thin gate oxide are improved by post gate anneal at higher temperatures. The leakage current decreases and the breakdown characteristics of the thin gate oxide are greatly improved. Particularly, the interface trap density at oxide/silicon decreases with the increase of annealing temperature, which is consistent with the behavior of polycrystalline silicon gate stress.