Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA

Abstract

SRAM-based FPGAs(Field Programmable Logic Arrays) always suffer SEU(Single Event Upset) in space applications, causing bit-flips in configuration memory. Especially, the trend of compression of semiconductor feature size increases the FPGA's vulnerability. In order to validate reliability and explore weakness of FPGA-based circuits, many testing mechanisms have been proposed. Previous studies have confirmed that SEU occurs in different on-chip resources will result in different consequences. And most circumstances are about logic altering and routing error of local regions. However, when configuration bits of DCM (Digital Clock Manager) flip, the clock outputs confusion is very likely to lead a large-scale circuit fault. Currently, few papers or reports have studied SEU of DCM. This paper presents a methodology to analyze DCM's SEU sensitivity. A process of bitstream parsing is employed first to find out the correspondence between DCM block and its configuration bits. Then SEU emulation in DCM is carried out by bitstream-based fault injection. Experimental results show that each clock output of DCM has its own, different degree of sensitivity. According analyzing the number and location of the output-specific fault bits, a general sensitive-bit distribution map is drawn. In addition, certain DCM attribute-accessing bits also be identified through fixed-point fault injection. This awareness will help to study DCM SEU mitigations or radiation hardening strategies in future work.