Abstract
All Programmable System-on-Chip (APSoC) devices are designed to provide higher overall system performance and programmable flexibility at lower power consumption and costs. Although modern commercial APSoCs offer a plethora of advantages, they are prone to experience Single Event Upsets. We investigate the impact of using different system architectures on an APSoC in the overall system failure rate. We consider different memory organization, different communication schemes, and different computing modes. Results show that there are several choices of architectures and resources to be chosen to implement an application in an APSoC, but there are logic resources that can increase or decrease the vulnerability of the entire system to failures in the application execution context.
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