Implementation of GNSS Receiver Hardware Accelerators in All-programmable System-On-Chip Platforms

Abstract

This paper reports the design and proof-of-concept implementation of hardware accelerator modules for a low power consumption and small form factor software-defined GNSS receiver using an all-programmable System-On-Chip (SoC) platform. An all-programmable SoC is a device that integrates the software reprogrammability of a CPU with the hardware reprogrammability of an FPGA. The presented approach takes advantage of the flexibility of software-defined radio technology, and the power efficiency and small form factor of a SoC, to implement a portable fully customizable GNSS receiver with the capability to process GNSS signals in real-time and to deliver GNSS products in standard formats. The SoC runs a free and open source software implementation of a multi-band, multi-system GNSS receiver released under the General Public License v3.0 and available in a public source code repository. However, the most computationally demanding tasks are offloaded to the FPGA and implemented as hardware acceleration modules. The hardware acceleration modules can take advantage of the inherent parallelism in the GNSS receiver signal processing functions. A review of the GNSS receiver architecture is presented, together with an overview of the software and a design description of the hardware accelerators in the SoC. A dual-band proof of concept GNSS receiver is exposed, together with some results.