Abstract
Tunnel field effect transistors (TFETs) are promising devices for low power applications. An analytical threshold voltage model, based on the channel surface potential and electric field obtained by solving the 2D Poisson’s equation, for strained silicon gate all around TFETs is proposed. The variation of the threshold voltage with device parameters, such as the strain (Ge mole fraction x), gate oxide thickness, gate oxide permittivity, and channel length has also been investigated. The threshold voltage model is extracted using the peak transconductance method and is verified by good agreement with the results obtained from the TCAD simulation.
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