Analytical modeling of asymmetric hetero-dielectric engineered dual-material DG-TFET

Abstract

The present work aims to incorporate the benefits of asymmetric hetero-dielectric engineering into the already popular dual-material double-gate tunnel field-effect transistor. Here, Poisson's equation in 2D, incorporating appropriate boundary conditions, is solved to obtain the surface potential variation along the channel while considering Young's popular parabolic approximation technique. From the potential profile, the electric field is derived, and the drain current expression is then extracted analytically, integrating the band-to-band tunneling generation rate over the tunneling region using Kane's model. The dependence of surface potential, electric field, and tunneling current on the device parameters is analyzed by varying the biasing voltages, gate oxide thickness, body thickness, and gate metal work function, demonstrating agreement with TCAD simulation results. The performance of the device is compared with the earlier-reported structure of the dual-material gate hetero-dielectric TFET on the basis of channel potential, electric field, and drain current. The proposed device exhibits higher ON-state current, better ON---OFF current ratio, and suppressed short-channel effects. The results also demonstrate the superiority of the graded dielectric over the single-dielectric and hetero-dielectric double-gate TFET.