Analytical model for the potential barrier height in depleted channel formed by P-N junctions

Abstract

P-N junction plays an important role in some semiconductor devices, such as bipolar junction transistor (BJT), metal- insulator-semiconductor field-effect transistor (MISFET) and junction field-effect transistor (JFET). However, the role of P-N junction in static induction device (SID) is different from other devices. SID is the typical example of semiconductor devices with depleted channel formed by two P-N junctions. Based on that, potential barrier has been formed in the channel, which is different from usual potential barrier in other semiconductor devices. The potential barrier controls electron movements in the parallel direction not in the vertical direction. In other words, the channel current is controlled by the potential barrier height, which is dependent on applied voltages. As a kind of junction devices, SID has been widely used in acoustic frequency, high frequency and microwave fields. Compared with other semiconductor devices, SID features high switching speed, high power, high pressure resistance, and strong anti-radiation which has been considered to be a promising power semiconductor device. The key principle of SID is that potential barrier height is dependent on applied voltages. As a result of that, the potential barrier model of SID has been proposed by Bulucea, but it doesn’t provide the clear analytical expression of potential barrier height with the device structure and applied voltages. Taking into account the defect existed in present potential barrier model of SID, a model of potential barrier in channel based on static induction transistor (SIT) was proposed. SIT as a typical example of SID is a type of power semiconductor device with vacuum-triode-like characteristics. The analytical expression of potential barrier height was deduced based on the analysis of device physics. Moreover, based on the assumed boundary conditions in the channel region and the depleted region bellow the channel region, the analytical expressions of barrier height was calculated by solving the simultaneous electrical potential distribution equations which were obtained by solving the Poison’s equation. The three-dimensional diagram of electrical potential distribution is obtained and it looks like a saddle. The model reflects the interdependency between the potential barrier and the material parameters, structure parameters and biases conditions. Gate-control efficiency of devices is dependent on channel length and channel width and drain-control efficiency is closely related to channel width and epitaxial impurity density. From the analytical expressions of barrier height, the voltage amplification factor can be improved by reducing drain-control efficiency and increasing gate-control efficiency. The two conditions are all dependent on the channel width. In order to verify the analytical expressions of barrier height, the numerical simulation of SIT was made at different conditions. Considering gate voltages, drain voltages, doping concentration in the epitaxial layer, channel length and channel width, the calculated potential barrier height based on the model is in good agreement with the numerical simulation results. The proposed model of potential barrier can be applied to the theoretical analysis of the I-V characteristics and structure characteristics of SID. Building accurate analytical model of potential barrier height can reduce manufacturing costs of semiconductor devices with depleted channel formed by P-N junction and improve device performance.