Analytical Layout Dependent NBTI Degradation Modeling Based on Non-Uniformly Distributed Interface Traps

Abstract

Previous studies reveal that interface traps induced by negative bias temperature instability (NBTI) are non-uniformly distributed under the channel of a pMOS device. The channel edges and lightly doped drain overlapping regions degrade more rapidly than the central channel. Consequently, smaller transistors suffer more severe degradation than that with larger size. In this paper, two analytical NBTI degradation models involving layout size have been derived: one for regular and the other for small size. Besides channel length and channel width, only two fitting parameters are introduced. Moreover, the proposed models have been validated and analyzed using the experimental distribution of interface traps. The results show that our proposed models can reflect the influence of layout size on NBTI degradation.