Abstract

Transconductance (gm) and differential conductance (gd) of ultrathin double-gate symmetric MOSFET is analytically investigated considering independent-gate architecture. Ortiz-Conde’s model is considered for the computation purpose, where symmetric potential is applied at both the gates. Centre potential is derived from gradual channel approximation, and modification is introduced at the drain current calculation. Following static and transfer characteristics, both type of conductances are calculated in presence of high-K dielectric. Results are compared with that obtained for SiO2 material, and subthreshold swing is also derived from the result. Simulated findings speak for sharp change in differential conductance and transconductance for ultrathin dielectric thickness, and peak of transconductance is attained at moderate gate bias. Very low subthreshold swing is observed at lower gate voltage, and 10–100 times lower gd is obtained along with approximately 2 times higher gm for equivalent EOT when compared with Ortiz-Conde model. Findings are significant for ID-DG MOSFET based nano-device circuit design.

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