Abstract

Thin film transistors (TFTs) fabricated on flexible and large area substrates have been studied with great interest due to their future applications. Recent studies have developed new semiconductors such as a-SiGe:H for fabrication of high performance TFTs. These films have important advantages, including deposition at low temperatures and low pressures, and higher carrier mobilities. Due to these advantages, the a-SiGe:H films can be used in the fabrication of TFTs. In this work, we present an analytical drain current model for a-SiGe:H TFTs considering density of states and free charges, which describes the current behavior at sub-and above- threshold region. In addition, 2D numerical simulations of a-SiGe:H TFTs are developed. The results of the analytical drain current model agree well with those of the 2D numerical simulations. For all characteristics of the drain current curves, the average absolute error of the analytical model is close to 5.3%. This analytical drain current model can be useful to estimate the performance of a-SiGe:H TFTs for applications in large area electronics.

Highlights

  • Thin film transistors (TFTs) are key devices to develop large area electronics applications such as active matrix liquid crystal displays (AMLCD) [1,2,3], wearable sensors [4,5] and passive tags RFID [6,7,8]

  • Threshold region of amorphous silicon-germanium (a-SiGe):H TFT operation, that is when VGS > VTH, free and localized charges are taken in to account due to the applied gate to source voltage generates a strong transversal electric field to the active layer which produces an accumulation of both carriers in the semiconductor/gate-insulator interface

  • In order to compare the results of our analytical drain current model, we develop 2D numerical

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Summary

Introduction

Thin film transistors (TFTs) are key devices to develop large area electronics applications such as active matrix liquid crystal displays (AMLCD) [1,2,3], wearable sensors [4,5] and passive tags RFID (radio frequency identification) [6,7,8]. Chen et al [17] reported an analytical drain current model for both triode and saturation region of operation for a-Si:H TFTs considering semiconductor density of states and an effective temperature approach. This model registered a high error between measurements and modeled results. We develop an analytical drain current model for a-SiGe:H TFTs that considers free and localized charges into semiconductor and its characteristic temperatures, which can represent the behavior at sub-threshold and above-threshold regions of operation without using fitting parameters.

Density of Estates of Amorphous Semiconductors
Analytical Drain Current Model
Total Analytical Drain Current Model
Results and Discussion
Bottom-gate top-contact coplanarTFT
Comparison
Absolute
Conclusions
Full Text
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