Abstract
Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive behavior has been widely investigated. Furthermore, gate-all-around (GAA) architecture to reduce short-channel effect is expected to be applied after Fin-FET technology. In this work, we proposed a compact model describing current–voltage (I–V) relationships of an NC GAA-FET with interface trap effects for the first time, which is a simplified model by taking proper approximation in each operating region. This is a surface potential-based compact model, which is suitable for evaluating the I–V characteristics for each operating region. It was validated that the proposed model shows good agreement with the results of implicit numerical calculations. In addition, by using the proposed model, we explored the electrical properties of the NC GAA-FET by varying the basic design parameters such as ferroelectric thickness (tfe), intermediate insulator thickness (tox), silicon channel radius (R), and interface trap densities (Net).
Highlights
IntroductionThe FinFET, having a multi-gate structure, has a limitation in scaling down at a technology node of 5 nm or less, so the introduction of a GAA type MOSFET structure is being considered to improve the gate control capability [1,2]
The ultra-thin semiconductor-on-insulator (UTSOI) structure that can effectively reduce the effect of the source–drain region on the channel region and the FinFET structure using a three-dimensional (3D) channel structure to improve gate controllability has been proposed to enable continuous scaling down of CMOS technology
Vn (y) at the source end and drain end in Equations (1) and (2), respectively. This method is the same approach used for compact modeling intrinsic channel regions in previous papers [15,19,24,25,26,27,28,29,31]
Summary
The FinFET, having a multi-gate structure, has a limitation in scaling down at a technology node of 5 nm or less, so the introduction of a GAA type MOSFET structure is being considered to improve the gate control capability [1,2] As well as such a multi-gate architecture, various device structures using a junction-less transistor structure or a channel material other than silicon have been proposed for various applications [3,4,5,6]. In addition to the introduction of new transistor architectures, reducing power consumption of the transistor has become a very important issue [7,8] This is because the density of power consumption inside the semiconductor chip increases exponentially as the number of semiconductor elements integrated in a unit area increases. Energy-saving ultra-low-power semiconductor technology is urgently required for semiconductor technology for Internet of Things (IoT) applications to Namkyu Cho
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