Abstract
Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed.
Highlights
IntroductionCompact and faster semiconductor transistors are required. To achieve this, the channel length of a device was reduced
With growing technology, compact and faster semiconductor transistors are required
Jimenez's work [12] we propose analytical simple drain current and threshold voltage model which can give useful and intuitive Equation for poly-Si GAA transistor
Summary
Compact and faster semiconductor transistors are required. To achieve this, the channel length of a device was reduced. Compact modeling was performed but using single-crystalline silicon and grain boundary effect which is represent using poly-silicon was not considered at all. The result of the model is not intuitive to implement SPICE simulation because of the complexity of the Equation and to understand the device operation and major electrical characteristics (e.g. threshold voltage) per operating domain. This issue is most often attributed to the use of GAA’s cylindrical coordinates and additional trap charge at the grain boundary in a poly-silicon channel. Analytical Drain Current Model for GAA Transistor with Poly-Crystalline Silicon Channel
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