Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer

Hyun Woo Kim,Daewoong Kwon

doi:10.3390/app10093054

Abstract

Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on the drain-side, that fringing field through the drain-side spacer increases ambipolar current and gate-to-drain capacitance, which degrades leakage property and switching response. Therefore, the drain-side low-κ spacer, which makes the low fringing field, is adapted asymmetrically with the source-side high-κ spacer. This asymmetric spacer results in the reduction of gate-to-drain capacitance and switching delay with the improved on-current induced by the source-side high-κ spacer.

Highlights

Over the past several decades, transistor dimensions have been continuously scaled down to make switching speed faster and to increase integration density, in accordance with Moore’s Law [1].device scaling induces many critical issues, such as short-channel effects (SCEs) and high leakage current
In the subthreshold region (0.0 V < VGS < 0.35 V), drain current is independent of κ values because tunneling mainly occurs between the source and tunnel region under the gate, without the effects of the fringing field through spacers
From VGS = 0.35 V, drain current starts to increase with increasing κ value

Summary

Introduction

Over the past several decades, transistor dimensions have been continuously scaled down to make switching speed faster and to increase integration density, in accordance with Moore’s Law [1]. That’s why additional source-to-channel junction optimization or low-κ spacer are required to improve the tunneling current. In tunnel FET with line-tunneling, fringing field effects improve the tunneling current without any junction optimization. This is because the area underneath the spacer is not source, but an epitaxially. Tunnel line-tunneling, fringing field effects improve the tunneling without any junction region underneath the underneath gates are adapted to is enhance gatebut controllability tunneling This is because the area the spacer not source, an epitaxiallyand grown silicon current channel drivability. Accurate analysis on the tunneling current, the dynamic nonlocal BTBT model is activated in the

Device

Results and Discussions

Conclusions