Analysis of Warpage and Stress Behavior in a Fine Pitch Multi-Chip Interconnection with Ultrafine-Line Organic Substrate (2.1D)

Abstract

The multi-chip module assembled with a composite layer of thin film on top of organic substrate is presented in this paper. This is a new-arising assembly technology with equivalent electrical performance of 2.5D package but much simplified supply-chain processes. We name this package as 2.1D package which converts the silicon interposer on the substrate. In this paper, the implementation of 2.1D technology on the monolithic, daisy-chain test vehicle is described. We employed thermal compression bonding (TCB) to mount two large dies with minimum 40 ?m-pitch micro bumps onto 45 x 45 mm organic substrate using 2/2 µm line width/space (L/S). Thermally induced misalignment, substrate warpage and the ELK (Extreme Low-K) stress during micro bumps joining with micro pads on substrate were evaluated. The mechanism of micro bump misalignment during solder formation has been experimentally and numerical validated by TCB and conventional mass reflow (MR) process. Finite element analyses were conducted to understand the 2.1D package warpage and stress behaviors, and hence defined better materials and process parameters. Simulation results showed that micro bump joining by TCB has 45% misalignment improvement as compared to MR process. In stress simulation results, the ELK layer stress of micro bump using TCB has a 59% reduction with reference to MR. In addition, the warpage behavior of fine-line organic substrate and 2.1D full package were measured using conventional shadow moire system. Results showed that the warpage variation of thin-film coated substrates was very stable within micro pads area that has less than 10 µm differences under high temperature period (120~260 °C). However, the package moire results showed that the thermally attaching of stiffener ring could significantly affect the global package warpage based on moire contours and warpage distributions. The reliability of this developed 2.1D, multi-chip test vehicle using TCB assembling processes was validated as well. This package passed MSL4 preconditioning and 1000 thermal cycles using G-conditions (-40~125 °C).