Analysis of Thermal Distribution in Low-Temperature Polycrystalline Silicon p-Channel Thin Film Transistors

Abstract

Degradation by Joule heating is one of the important issues for realizing systems on a panel. We have investigated the thermal distribution of low-temperature polycrystalline silicon (poly-Si) p-channel thin-film transistors (TFTs) using an infrared imaging system. In order to design optimum circuits in which Joule heating is taken into account, a systematic analysis of Joule heating focusing on gate size and bias voltage dependences was performed. Using TFTs with channel lengths of 50 and 6 µm, thermal distributions were compared under linear and saturation regions for drain current. The asymmetrical distribution observed in the 50-µm-channel TFT under the saturation condition was small in the 6-µm-channel TFT. Different distributions were was analyzed using the simulation results obtained with a device simulator. Furthermore, maximum temperature was measured as a function of input power by varying gate and drain voltages. Degradation was also measured using p-channel TFTs with various gate sizes. A negative threshold voltage shift was observed with increasing stress time. It was revealed that the maximum temperature was dominated by the input power independent of bias voltage or gate length and that the main cause of this shift was Joule heating. This result also indicated that we do not have to take the impact ionization caused by the electric field distribution into account.