Abstract
The use of gate-to-drain capacitance ( C gd) measurement as a tool to characterize hot-carrier-induced charge centers in submicron n- and p-MOSFET’s has been reviewed and demonstrated. By analyzing the change in C gd measured at room and cryogenic temperature before and after high gate-to-drain transverse field (high field) and maximum substrate current ( I bmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface states were found to be acceptor states at top half of band gap for n-MOSFETs and donor states at bottom half of band gap for p-MOSFETs. In general, hot electrons are more likely to be trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states. Also, we have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Q ot, through gate-to-substrate capacitance ( C gb) measurement. This method is simple to implement and does not require additional information from simulation or detailed knowledge of the device’s structure.
Published Version
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