Analysis of the Electrical Performance of a Layer Stackup Design for Memory Socket Boards

Abstract

As the operation speed of semiconductor products increases, a test technique is required to implement a high-speed operation at a low-cost. In this paper, memory socket boards are designed by applying a layer stackup reduction and a low-cost dielectric. In the layer stackup design, the two layers are reduced through arrangement of the power planes and a split design. A low-cost dielectric based on FR4 epoxy was applied in the board. Electrical performance changes on the board were analyzed and compared. Although the insertion loss of the DQ5 line on the board with layer stackup reduction showed almost no difference, the VDDQ-VSS impedance increased in some frequency bands. The timing aperture and power supply noise characteristics remained almost the same, which had no substantial effect on high-speed operation of the board. The insertion loss of the DQ5 line on the board with the low-cost dielectric showed a difference in the high-frequency band, but the VDDQ-VSS impedance improved. The timing aperture characteristics were lower, but the performance under power supply noise improved in the eye-diagram simulation.