On-chip design techniques for reducing power supply noise effects on ADC with chip-PCB hierarchical structure

Abstract

In this paper, we propose the on-chip design techniques for controlling Power Supply Noise (PSN) effects on Analog-to-Digital Converter (ADC) with chip-Printed Circuit Board (PCB) hierarchical structure interconnected by bonding wires. There are two steps for explaining the proposed design technique. First, we explain what the PSN coupling path is on ADC. The PSN will couple from noise source to noise victim via power distribution network and circuit path. Second, we propose how we can reduce the noise coupling effects. The comparator is essential circuit to ADC and most sensitive circuit to PSN in ADC. Therefore, it is important to reduce the noise coupling effects on comparator for designing ADC which is non-sensitive to PSN. The comparator has two input nodes, and the differential voltage between two input nodes affect to ADC output. The impedance imbalance between two comparator inputs is the reason why the comparator is sensitive to PSN. So, the technique which is for balancing two input impedance is important to reduce PSN effects. We consider chip-PCB components to estimate two input impedance, because the two input impedances are affected by chip-PCB hierarchical structure. If we control the impedance of each input, we can design the ADC which is nonsensitive to PSN at the targeted frequency. We demonstrate the proposed technique based on simulation by PSN whose frequency swept from 1MHz to 3GHz.