Analysis of the Back-Gate Effect on the on-State Breakdown Voltage of Smartpower SOI Devices

Abstract

This paper discusses the impact of the back-gate bias on the on-state drain breakdown voltage of high-voltage silicon-on-insulator (SOI) MOSFETs. This is mandatory in order to understand the physical mechanisms behind the limitations of the safe operation area (SOA) of SOI power devices. The back-gate electrode of the SOI material will add an additional dimension to the SOA, thereby causing further reliability constraints on the circuit design. For small and negative back-gate bias, the SOA is limited by the on-state breakdown whereas the off-state breakdown sets the limit for positive back-gate bias. For the first time, an analytical model of the breakdown voltage covering the reasonable back-gate voltage range is presented providing a first step toward a closed form circuit simulation of this effect. It is shown that the back-gate potential impacts on the breakdown behavior by modulating the carrier distribution in the drift region, the base transport factor of the parasitic bipolar transistor, and the drift region resistance. Moreover, it is shown that avalanche multiplication is the limiting breakdown mechanism for lateral SOI power devices