Analysis of subthreshold swing and internal voltage amplification for hysteresis-free negative capacitance FinFETs

Abstract

We present the device design guideline for hysteresis-free negative capacitance FinFETs (NC-FinFETs) to enhance the internal voltage amplification (A v ) and reduce the subthreshold swing (SS). Av can be increased by increasing fin width (W fin ), coercive field (Ec), and thickness of the ferroelectric layer (T fe ), and Ay can also be enhanced by reducing EOT, channel length (L ch ), buried oxide thickness (T box ), fin height (H fin ) and remnant polarization (P 0 ). The subthreshold swing improvements of NC-FinFETs over FinFETs become larger as A V increases. With the same channel length, compared with the NC-FinFET without underlap design, NC-FinFET with underlap design exhibits better capacitance matching and larger A V , hence showing larger subthreshold swing improvement and on-current improvement over FinFET. At shorter L ch (= 12.5nm), NC-FinFETs with underlap design exhibit 73.6% improvements in intrinsic delay compared with the FinFETs due to its larger effective drive current.