Analysis of simulation approaches for the breakdown characteristics of SOI high-voltage PMOS in a fixed power supply

Abstract

A novel simulation approach for the breakdown characteristics of SOI high-voltage (HV) PMOS in a fixed power supply application is proposed. The different optimized parameters for the SOI HV PMOS can be achieved by the conventional and proposed simulation approaches. A SOI variation of lateral doping (VLD) field PMOS, which is widely used in the level-shift circuit is investigated by the conventional and novel simulation approaches. For the level-shift circuit with power supply of 400V, the breakdown voltage (BV) of the optimized SOI VLD field PMOS increases from 520V with the conventional simulation approach to 646V with the proposed simulation approach. Moreover, the corresponding optimized doping concentration of p-drift region with the proposed approach is higher than that with the conventional approach, thus greatly reducing the specific on-resistance (Ron,sp). The SOI VLD field PMOS actually has a more robust breakdown voltage and lower Ron,sp in the fixed power supply. The BV and Ron,sp of SOI HV PMOS can be truly reflected and the effect of reduced bulk field (REBULF) is revealed in the fixed HV power supply by employing the novel simulation approach.