Analysis of short circuit current loss in rear emitter crystalline Si solar cell

Tatsuro Watahiki,Shinya Nishimura,Yumiko Kobayashi,Mikio Yamamuka,Hidetada Tokioka,Daisuke Niinobe,Kunihiko Nishimura,Takayuki Morioka

doi:10.1063/1.4951003

Abstract

Short circuit current (Jsc) loss in rear emitter crystalline Si solar cell is analyzed in detail by a 2D device simulation and compared with the experimental results. There is a significant loss in Jsc for the rear emitter n-Si solar cell with an n-type doped front surface field (FSF) when the base substrate resistivity is low. It is due to an increase in recombination in the FSF region led by a less barrier height for minority carriers with a lower substrate resistivity. The barrier height less than 0.1 eV causes large loss in Jsc. To achieve higher Jsc for the cells with FSF, the control of the doping concentration in FSF, the substrate thickness, and the barrier height for the minority carriers are important. A rear emitter heterojunction Si solar cell with an amorphous Si passivation layer shows no substrate resistivity dependence on Jsc since an amorphous Si possess a higher barrier height and a long bulk lifetime of more than a few milliseconds.

Highlights

The n-type crystalline Si solar cell possesses a potential to achieve a very high energy conversion efficiency due to a higher bulk lifetime, a larger thermal tolerance, and a less impact of metallurgical impurities on the bulk lifetime than p-type crystalline Si.[1,2] We have developed the n-type crystalline Si solar cell with PERT (Passivated Emitter Rear Totally diffused) structure and achieved an efficiency of over 21%.3 On the other hand, a very high efficiency of over 24% is reported for a heterojunction Si solar cell.[4]
There is a significant loss in Jsc for the rear emitter n-Si solar cell with an n-type doped front surface field (FSF) when the base substrate resistivity is low
It is due to an increase in recombination in the FSF region led by a less barrier height for minority carriers with a lower substrate resistivity

Summary

INTRODUCTION

The n-type crystalline Si solar cell possesses a potential to achieve a very high energy conversion efficiency due to a higher bulk lifetime, a larger thermal tolerance, and a less impact of metallurgical impurities on the bulk lifetime than p-type crystalline Si.[1,2] We have developed the n-type crystalline Si solar cell with PERT (Passivated Emitter Rear Totally diffused) structure and achieved an efficiency of over 21%.3 On the other hand, a very high efficiency of over 24% is reported for a heterojunction Si solar cell.[4]. We have investigated on the heterojunction Si solar cell and reached the efficiency of 23.46% with a rear emitter (RE) structure.[5] An RE Si solar cell has an emitter on the rear side of the Si substrate against the incoming sun light. This RE structure has several advantages to the front-emitter (FE) structure.[6,7] Since the emitter is located on the rear side, the emitter has less impact on the optical loss and it has more freedom for the design of structure, such as a surface morphology, a sheet resistance, and a grid pitch.

EXPERIMENT

Â 1019 5 Â 1019 8 Â 1014–9 Â 1015

Comparison between experiment and calculation for RE Si solar cell

Â 1012

Reduction of Jsc loss

CONCLUSION