Abstract

GaN based technologies are promising in terms of electrical performances for power and high frequencies applications and their reliability assessment remains a burning issue. Thus, a good understanding of their degradation mechanisms is required to warranty their reliability. In this paper, an electrical parasitic effect has been observed on the gate–source diode forward characteristics of a set of devices under HTRB stress carried out at 175°C up to 4000h. This parasitic effect has been attributed to lateral surface conduction and correlated with EL signature under diode forward biasing conditions but not under transistor pinch-off biasing conditions. Then, physical analyses have pointed out the formation and growing over time of pits and cracks at the gate edge on the drain side.

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