Abstract
The analysis of random variation in the performance of Floating Gate Metal Oxide Semiconductor Field Effect Transistor (FGMOSFET) which is an often cited semiconductor based electronic device, operated in the subthreshold region defined in terms of its drain current (ID), has been proposed in this research.IDis of interest because it is directly measurable and can be the basis for determining the others. All related manufacturing process induced device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account. The analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy. By using such result, the strategies for minimizing variation inIDcan be found and the analysis of variation in the circuit level parameter of any subthreshold FGMOSFET based circuit can be performed. So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit.
Highlights
The FGMOSFET in subthreshold region has been found to be an extensively utilized semiconductor based electronic device for low voltage/low power circuits [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16]
Similar to the ordinary Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the subthreshold FGMOSFET is more susceptible to these variations than that in the above-threshold region and its drain current (ID) has been found to be the key circuit level performance as it is directly measurable and can be the basis for determining the others according to their relationships
Based on the proposed analysis result, it has been found that the subthreshold FGMOSFET under low voltage/low power operating condition is subjected to large ΔID and the P-type subthreshold FGMOSFET has been found to be a more preferable device as it is more robust to the manufacturing process induced device level random variations than its N-type counterpart
Summary
The FGMOSFET in subthreshold region has been found to be an extensively utilized semiconductor based electronic device for low voltage/low power circuits [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16]. The concept of variability aware design has been applied to such low voltage/low power circuits for handling the effects of the manufacturing process induced device level random variations [6, 10,11,12,13,14,15,16]. The examples of these variations are the variation in channel width (W) and channel length (L) and so forth. By using the obtained result, the strategies for minimizing ΔID can be found and the analysis
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