Analysis of p+-n Junction Capacitance with Three-Dimensional Impurity Profiling Method Using Scanning Tunneling Microscopy

Abstract

The p+-n junction capacitance characteristics have been analyzed by a novel three-dimensional impurity profiling method using chemical etching and scanning tunneling microscopy. The calculated capacitance-voltage characteristics for plane and side-wall capacitances agree better with the measured characteristics than does the case with conventional SIMS analysis. It is found that the C-V characteristics for side-wall capacitance scarcely depend on the impurity profile. Moreover, the obtained side-wall capacitance value enables a more accurate simulation of circuit performance. These results show that the proposed STM profiling method is a promising tool for the characterization of submicrometer devices.