Analysis of Parasitic Front-end Capacitance and Thermal Resistance in Hybrid Flip-chip-bonded GaAs SEED/Si CMOS Receivers

Abstract

Smart pixels[1] consisting of photodetectors, electronic circuitry, and E/O converters utilizing free-space optical interconnections show promise to relieve the interconnection bottleneck in computing and switching systems.[2] To reduce the propagation delay through a smart pixel, the receiver requires a fast response, hence it is essential to reduce the front end capacitance (Cin). Cin has three main components: the photodiode active area, the amplifier input, and the stray interconnect capacitance (Cs). The FET-SEED technology minimizes Cs through the monolithic integration of photodetectors, modulators and electronic circuitry.[3][4]] However, current system demonstrations using FET-SEEDs have been limited to using medium scale integration (MSI) smart pixel arrays. Hybrid integration of VLSI Si CMOS electronic circuitry with photodetectors, modulators, or emitters is an attractive approach in obtaining VLSI smart pixels in the near term.