Analysis of out-of-sequence problem and preventative schemes in parallel switch architecture for high-speed ATM network

Abstract

The parallel switch architecture combines advantageously a parallel plane method with a bit-parallel conversion scheme in VLSI implementation of ATM switches with the capability of handling unlimited external trunk speed. However, the parallel architecture encounters out-of-sequence problems owing to various possible switching paths. The authors analyse the out-of-sequence performance dependency on the trunk utilisation, the total number of virtual channels/trunk, and the number of parallel switch planes. They then propose two parallel switches equipped with preventive schemes for avoiding cells delivered out-of-sequence. By using the method of cascading virtual channel routing networks at input lines of the switch planes, the large speed reducing effect to support trunks at speeds of several Gb/s can be achieved in ATM-based parallel switch design. Also, the out-of-sequence problem is basically eliminated, and additional delay can be reduced to a negligible level.